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40 Gb/s all-optical packet clock recovery with ultrafast lock-in time and low inter-packet guardbands

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Abstract

We demonstrate a 40 Gb/s self-synchronizing, all-optical packet clock recovery circuit designed for efficient packet-mode traffic. The circuit locks instantaneously and enables sub-nanosecond packet spacing due to the low clock persistence time. A low-Q Fabry-Perot filter is used as a passive resonator tuned to the line-rate that generates a retimed clock-resembling signal. As a reshaping element, an optical power-limiting gate is incorporated to perform bitwise pulse equalization. Using two preamble bits, the clock is captured instantly and persists for the duration of the data packet increased by 16 bits. The performance of the circuit suggests its suitability for future all-optical packet-switched networks with reduced transmission overhead and fine network granularity.

©2005 Optical Society of America

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Figures (4)

Fig. 1.
Fig. 1. Experimental setup.
Fig. 2.
Fig. 2. Pulse traces of (a) three input data packets, (b) corresponding FPF output, (c) recovered clock packets at time base 500 ps/div and (d) single packet, (e) FPF output and (f) single recovered clock packet at time base 200 ps/div. The vertical scale is 335µW/div.
Fig. 3.
Fig. 3. Eye diagrams of (a) incoming data, (b) FPF output and (c) extracted clock at 50 ps/div and (d) incoming data, (e) FPF output and (f) recovered clock at 10 ps/div. The vertical scale of upper row is 390µW/div and the lower row vertical scale is 500µW/div.
Fig. 4.
Fig. 4. Recovered clock (a) optical spectrum and (b) autocorrelation trace with sech fitting.
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